1. Technical Field
The present disclosure relates to package substrates, and, relating to a package substrate having an interposer embedded therein and a method of fabricating the package substrate.
2. Description of Related Art
With the growing demands for low-profiled and compact-sized electronic products, a chip has to have a great layout density, and the pitches of contacts on the chip are dramatically reduced accordingly (e.g., a few nanometers). The conductive contacts of a flip-chip package substrate have pitches as great as a few micrometers. Such a package substrate cannot be applied to the modern chips and electronic products.
In order to solve the above-mentioned problems, a silicon interposer is added between the package substrate and the semiconductor chip, metal is electroplated in the silicon interposer to form through-silicon vias (TSV), a redistribution layer (RDL) is then formed on the TSVs, conductive bumps are disposed on one side of the silicon interposer via the end surfaces of the through-silicon vias so as to be electrically connected to the contacts of a package substrate that have greater pitches, and the other side of the silicon interposer is electrically connected to the contacts of a chip that have smaller pitches via conductive pads on a topmost layer of the redistribution layer. In this manner, the package substrate can be electrically connected to a chip that has contacts of a great layout density.